1. Field of the Invention
The invention relates to generally to semiconductor structures and processes, and more particularly to a reduced junction capacitance semiconductor structure and a method of manufacture.
2. Background
Advances in semiconductor process technology and digital system architecture have led to integrated circuits having increased operating frequencies. Unfortunately, higher operating frequencies result in undesirable increases in power consumption. Power consumption is a significant problem in integrated circuit design generally, and particularly in large scale, high speed products such as processors and microprocessors.
Nonetheless, the trend of integrating more functions on a single substrate while operating at ever higher frequencies goes on unabated.
One way to improve integrated circuit performance, is by reducing the loading capacitance of metal-oxide-semiconductor field effect transistors (MOSFETs). Transistor loading capacitance generally has three components, intrinsic gate capacitance, overlap capacitance, and junction capacitance. To reduce junction capacitance, MOSFETs have been constructed on an insulating substrate. This is often referred to as silicon-on-insulator (SOI). Typical SOI processes reduce junction capacitance by isolating junctions from the substrate by interposing a thick buried oxide layer. However, short-channel MOSFETs constructed with thick buried oxide layers isolating their junctions from the substrate, tend to have poor punch-through characteristics, poor short-channel characteristics and other effects related to the floating body.
What is needed is a semiconductor structure having reduced junction capacitance and while maintaining good device characteristics. What is further needed is a method of manufacturing such a semiconductor structure.